Technical Field
The present disclosure relates to the fabrication of nanometer-sized integrated circuit planar field-effect transistor (FET) devices.
Description of the Related Art
As technology nodes for integrated circuits scale below 10 nm, maintaining precise control of various electrical characteristics in semiconductor devices becomes increasingly more challenging. Such semiconductor devices include, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). A MOSFET is a three-terminal switching device that includes a source, a gate, and a drain. MOSFETs are interconnected by a network of wires through contacts to each of the source, drain, and gate terminals.
When a voltage exceeding a selected threshold voltage (Vt) is applied to the MOSFET gate, the device switches on so that an electric current flows through a channel between the source and the drain. The value of Vt depends, in part, on the characteristic energy band structure of the semiconductor material. The source and drain regions are typically doped with ions that serve as charge reservoirs for the device. Device performance parameters such as switching speed and on-resistance are largely dependent upon control of doping concentrations and depth profiles of the dopants in the substrate following implantation and annealing of the implanted regions at high temperatures.
For many years, device designers strived to fashion the tips of dopant profiles so as to reduce the channel length, thereby increasing the switching speed of the device. However, when the channel length between the doped source and drain regions is reduced so far as to be comparable to their depth, current may leak through such a short channel, causing the device to turn on at an applied voltage that is less than the threshold voltage. Off-state leakage is thus an example of a short channel effect (SCE). Present technology challenges include preventing off-state leakage and other short channel effects such as drain-induced barrier lowering (DIBL), and controlling a device characteristic referred to as a sub-threshold slope (SS). DIBL occurs when a high drain voltage causes the transistor to turn on prematurely, even though the Vt electric potential barrier has not been overcome. DIBL occurs because in a short channel device, the drain voltage has a greater influence over device performance, due to its closer proximity to the center of the channel. A device having a steep SS transitions faster from an off state to an on state. Thus, controlling the SS can be another important factor in improving device performance.
Strained silicon transistors address some of these challenges by replacing bulk silicon in the source and drain regions, or in the channel region, with epitaxially grown silicon compounds such as, for example, epitaxially grown silicon germanium (SiGe). Introducing strain into the silicon crystal of a MOSFET tends to increase charge mobility in the channel region, thereby improving performance without the need for a short channel. However, strained silicon and other new technologies fail to address all of the technology challenges listed above.
Another FET technology that addresses short channel effects entails use of a recessed gate, as described in U.S. Patent Application Publication US201210313144, by the same inventor as in the present patent application. Other examples of recessed gate architectures are found in U.S. Pat. No. 6,630,385 to Bin Yu. A recessed gate device features a metal gate buried between the source and drain regions, and a current channel below the recessed gate, near the lower boundaries of the source and drain regions where they meet the buried oxide layer (BOX). Whereas in a conventional FET, the channel length is governed by implant profiles of the source and the drain regions, in a recessed gate device, the channel length is set by the width of the gate, which is easier to control. The channel length in a recessed gate device is further tuned by adjusting the width of sidewall spacers on either side of the gate. Thus, short channel effects can be avoided by fabricating a channel having a selected minimum length. When the channel is bounded above by the recessed gate and below by a buried oxide layer, the gate maintains tighter control over the charge flowing therein.